Process for manufacturing a multi layer bumped semiconductor dev

Details Process for manufacturing a multi layer bumped semiconductor dev Process for manufacturing a multi layer bumped semiconductor dev

1996-09-19

1999-01-26

Graybill, David

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

438118, 438613, E02F 365

Patent

active

058638121

ABSTRACT:
A method for fabricating a chip size package is provided. The method includes the step of forming a laminated substrate which consists of a dielectric layer and a highly conductive layer disposed thereon. Holes are drilled into the dielectric layer. A desired pattern is applied to the conductive layer. A chip structure is formed which consists of a silicon die and an insulating layer disposed thereon. Gold bumps are applied to the top surface of the bonding pads. The laminated substrate is bonded to the chip structure via the holes and gold bumps. A solder mask is applied over the top surface of the conductive layer of the laminated substrate so as to form selective solder areas. Finally, solder balls are attached to the selective solder areas.

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