Arbitrator circuit and technique for use in a digital computing

Details Arbitrator circuit and technique for use in a digital computing Arbitrator circuit and technique for use in a digital computing

1983-04-14

1986-04-29

Chan, Eddie P.

Boots, shoes, and leggings

3408255, G06F 1318

Patent

active

045861285

ABSTRACT:
In a digital computing system having multiple controllers, multiple memories and multiple memory interfaces, wherein each controller periodically requests access to a memory, an arbitrator device in the memory interfaces is disclosed, which includes circuitry for granting poll requests of the controllers in a prescribed manner of protocol. The arbitrator of this invention includes an input gating structure, a priority encoder, a poll request register and a grant register. During an arbitration cycle, upon reception of one or more active poll signals from the bus controllers, the respective grant signal of the highest priority active poll is immediately returned to the controller. All non-granted poll inputs are disabled so as to lock out any subsequent poll signals. This provides the granted controller exclusive use and control of the data bus between the controller and the memory interface.

REFERENCES:
patent: 4229791 (1980-10-01), Levy et al.
patent: 4245307 (1981-01-01), Kapeghian et al.
patent: 4423384 (1983-12-01), De Bock
patent: 4453214 (1984-06-01), Adcock
patent: 4472712 (1984-09-01), Ault et al.

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