Method of synthesizing synchronized circuit modules in an integr

Details Method of synthesizing synchronized circuit modules in an integr Method of synthesizing synchronized circuit modules in an integr

1996-11-20

1999-11-09

Butler, Dennis M.

Boots, shoes, and leggings

395551, G06F 1500

Patent

active

059800917

ABSTRACT:
An integrated circuit chip is fabricated as several circuit modules that are synchronized with a clock signal, by the following steps. Initially, a hardware description language is used to describe a functional behavior for a first module on the chip which generates an intermodule signal, and describe a functional behavior for a second module on the chip which processes the intermodule signal. Thereafter, a slow circuit embodiment of the first module is synthesized with port timing constraints which permit the intermodule signal to be generated in twice the cycle time T.sub.CY of the clock signal, and a slow circuit embodiment of the second module is synthesized with port timing constraints which permit the intermodule signal to be processed in twice the cycle time of the clock. Then, a timing analysis program is run on the slow circuit embodiment of the first and second modules to thereby obtain a first delay .DELTA..sub.1 in which the intermodule signal is actually generated, and obtain a second delay .DELTA..sub.2 in which the intermodule signal is actually processed. Subsequently, a fast circuit embodiment of the first module is synthesized which generates the intermodule signal within a delay of (T.sub.CY)(.DELTA..sub.1).div.(.DELTA..sub.1 +.DELTA..sub.2) and a fast circuit embodiment of the second module is synthesized which processes the intermodule signal within a delay of (T.sub.CY)(.DELTA..sub.2).div.(.DELTA..sub.1 +.DELTA..sub.2).

REFERENCES:
patent: 5095454 (1992-03-01), Huang
patent: 5426591 (1995-06-01), Ginetti et al.
patent: 5521837 (1996-05-01), Frankle et al.
patent: 5726902 (1998-03-01), Mahmood et al.

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