Method and apparatus for delaying writing back the results of in

Details Method and apparatus for delaying writing back the results of in Method and apparatus for delaying writing back the results of in

1990-02-14

1993-06-22

Shaw, Dale M.

395375, G06F 9312, G06F 938

Patent

active

052222403

ABSTRACT:
The present invention describes an integer execution unit register file having one fewer write port by employing delayed writeback for data transfer instructions in a high speed processor. The integer execution unit comprises a register file with 32 separate registers, each 32-bits long. The register file is a write through register file. A four-stage instruction pipeline is employed to execute all integer instructions. The four stages are (1) Fetch, (2) Decode, (3) Execute, and (4) Writeback. For data transfer type of instructions such as, a load instruction, one extra instruction stage is usually required. The prior art processors add one extra write port to accommodate such data transfer type of instructions. The present invention delays the writing of the data transfer type instruction until the writeback stage of the next data transfer instruction. The result of the data transfer type instruction returns at the end of the writeback stage. The result is held in a temporary register. All references to the result of such a data type transfer instruction will be bypassed from the temporary register to the proper execution block. The data from the temporary register is written back into the register file only at the writeback stage of the next data transfer type instruction. Thus, the present invention resolves the conflict of resources for the write port and at the same time saves one port to the register file. The present invention not only reduces the amount of silicon area required for high speed processors, it also reduces the layout complexity. It follows that the present invention improves the overall speed of the processor.

REFERENCES:
patent: 4734852 (1988-03-01), Johnson et al.
patent: 4926323 (1990-05-01), Baror et al.
patent: 5123097 (1992-06-01), Joyce et al.
patent: 5148529 (1992-09-01), Ueda et al.

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