Memory management system

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Details

G06F 946

Patent

active

045450161

ABSTRACT:
A memory management system for providing memory protection for various programs running in a computer such as a 16-bit multi-tasking computer system. The scheme of the present invention provides address translation so as to provide separation of memory spaces. In this connection, each program in the machine has associated therewith, two numbers including an offset number and a limit number. Each program is written so that its base starting address is at the same predetermined address, preferably zero. The address space for each program is separated in memory by adding the offset number for that program to the base address to provide the physical address number. The program is prevented from accessing any memory area outside of its allotted area by comparing the sum of the offset and processor addresses to the limit number. If the result is less than the limit number, the computed address is valid, and if it is outside the limit number then the computed address is considered invalid and an error routine is initiated.

REFERENCES:
patent: 4300192 (1981-11-01), Couleur et al.
patent: 4333144 (1982-06-01), Whiteside et al.
patent: 4633097 (1982-12-01), Amano et al.

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