Pseudo logarithmic analog step adder

Details Pseudo logarithmic analog step adder Pseudo logarithmic analog step adder

1991-06-03

1993-06-22

Ng, Jin F.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307492, 307529, 328143, G06G 724, G06G 712, G06G 700

Patent

active

052219070

ABSTRACT:
A signal to be scaled is supplied to three parallel amplifiers with gains of 0.1, 1, and 10, which each amplify the input simultaneously. The amplifiers are designed so that their output is limited to 1 volt regardless of the level of voltage at their input. This allows the lower magnitude portions of the signals to be amplified without amplifying the higher magnitude signals. The output of the amplifiers are summed together to provide the scaled signal.

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patent: 4972512 (1990-11-01), Garskamp
patent: 4990803 (1991-02-01), Gilbert
patent: 5012140 (1991-04-01), Bateman
Damijanovic, "Quasi-logarithmic system for measuring dc current", Aug. 1976, pp. 33-35.

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