Method and apparatus for self-testing of floating point accelera

Details Method and apparatus for self-testing of floating point accelera Method and apparatus for self-testing of floating point accelera

1983-11-07

1986-04-15

Atkinson, Charles E.

Excavating

364200, G06F 1122

Patent

active

045832226

ABSTRACT:
A mechanism for continually testing a first processor element in a suitable multiprocessor system in which at least first and second processor elements are connected to a common input bus to concurrently receive the same opcodes and operands. Both processors decode the opcodes; when an opcode indicates an operation to be performed by the second processor, the first processor responds by executing a diagnostic operation during the second processor's execution cycle, instead of remaining idle for that time. The particular diagnostic operation to be performed is selected from among a multiplicity of available diagnostic operations. The selection is dependent on the instruction to be executed by the second processor; that is, in order to not slow down the overall execution rate of the system, a diagnostic operation is chosen whose execution time is somewhat shorter than the execution time of the instruction being performed by the second processor. Operand data supplied for the second processor's operation may be used as test data by at least some of the diagnostic operations for the first processor, to facilitate detection of bits forced to a zero or one value. Both data paths and control logic of the first processor are checked during the execution of each instruction intended for another processor, without slowing overall system response or adding more than an insignificant marginal cost. The diagnostic system is self-executing and is completely transparent to the programmer.

REFERENCES:
patent: 3916178 (1975-10-01), Greenwald
patent: 4228496 (1980-10-01), Katman et al.
patent: 4387427 (1983-06-01), Cox et al.
patent: 4443849 (1984-04-01), Ohwada
patent: 4462075 (1984-07-01), Mori et al.

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