DMOS with high-resistivity gate electrode

Details DMOS with high-resistivity gate electrode DMOS with high-resistivity gate electrode

1983-10-06

1986-04-29

Edlow, Martin H.

357 41, 357 59, 357 231, 357 24, 357 53, 357 238, H01L 2978, H01L 2904, H01L 2704, H01L 2940

Patent

active

045860645

ABSTRACT:
By the use of high-resistivity polycrystalline silicon (poly) in MIS elements, a depletion layer can be formed in the poly material which brings about an electric decoupling between the poly (gate) and the underlying semiconductor body. This effect can be utilized advantageously in various circuit elements, such as in CCD's, in order to obtain a favorable potential distribution in the substrate; in MOS transistors in order to reduce the parasitic capacities; and in high-voltage devices in order to increase the breakdown voltage at the edge of the field plate (resurf).

REFERENCES:
patent: 3932882 (1976-01-01), Berger
patent: 3943545 (1976-03-01), Kim
patent: 4157557 (1979-06-01), Sato et al.
patent: 4270137 (1981-05-01), Coe
Whelan et al., "Resistive-Insulated-Gate Arrays and their Applications . . . " Phillips Research Reports, vol. 30, No. 6, Dec. 1975, pp. 436-482.
Hu et al., "A Resistive-Gated IGFET Tetrode," IEEE Transactions on Electron Devices, vol. ED-18, No. 7, Jul. 1971, pp. 418-425.

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