Method for the 3D interconnection of packages of electronic comp

Details Method for the 3D interconnection of packages of electronic comp Method for the 3D interconnection of packages of electronic comp

1995-05-09

1997-06-24

Vo, Peter

Metal working

Method of mechanical manufacture

Electrical device making

29417, 29831, 29841, 216 65, 26427214, H05K 328, H05K 330, H05K 336

Patent

active

056407602

ABSTRACT:
In a method for the interconnection of stacked packages, each of the packages encapsulating, for example, a semiconductor chip containing an integrated circuit, a memory for example, the packages provided with pins are mounted on a printed circuit board. The printed circuit boards are stacked and fixedly joined with one another by means of a coating, for example a resin coating. The stack is sliced through so as to form bars, the pins of the packages being electrically connected to the side surfaces of the bars by means of the tracks of the printed circuit boards. The connection of the packages to one another is done on the side faces of the bars. The bars are then sliced through to obtain unit blocks of stacked packages.

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