Memory using multiplexed row and column address lines

Details Memory using multiplexed row and column address lines Memory using multiplexed row and column address lines

1982-12-22

1985-09-10

Fears, Terrell W.

Static information storage and retrieval

Addressing

365189, G11C 1140

Patent

active

045410780

ABSTRACT:
A memory of rows and columns of memory cells uses a multiplexed input address buffer having output row-column address lines which are coupled to a multiplexer and to column decoders. The multiplexer is coupled to row address decoders and serves to selectively couple the address lines to the row decoders. The address lines typically first carry row address information and then column address information. The use of a common portion of the address lines to couple the address buffer to the column decoders and multiplexer tends to reduce the overall size of the memory and thereby increases yield and reduces cost.

REFERENCES:
patent: 3760384 (1973-09-01), Krolikowski et al.
patent: 3806880 (1974-04-01), Spence
patent: 4050061 (1977-09-01), Kitagawa
patent: 4200917 (1980-04-01), Moench
patent: 4275312 (1981-06-01), Saitou et al.
patent: 4394753 (1983-07-01), Penzel

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