Data clocking circuitry for a scanning apparatus

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Details

364519, 350 65, 350 68, 358208, 346108, H04N 122, G06K 1512

Patent

active

045410615

ABSTRACT:
Clocking circuitry for providing clocking signals in accordance with a preprogrammed sequence of rates. An addressable memory is included having data defining such rates with a voltage controlled oscillator (VCO) controlled via data from the addressable memory. An address producing means is controlled by the clocking signals of the VCO to provide an address signal for the memory in response to each clocking signal. The clocking circuitry is used with a moving mirror for a laser printer apparatus, the mirror having a known repetitive movement which is used in establishing the preprogrammed sequence of rates.

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patent: 4355860 (1982-10-01), Lavallee et al.
patent: 4358789 (1982-11-01), Confer
patent: 4386271 (1983-05-01), Chiang et al.
patent: 4410234 (1983-10-01), Mikami et al.

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