Microprocessor architecture employing efficient operand and inst

Details Microprocessor architecture employing efficient operand and inst Microprocessor architecture employing efficient operand and inst

1981-09-21

1985-09-10

Heckler, Thomas M.

Boots, shoes, and leggings

G06F 930

Patent

active

045410453

ABSTRACT:
A two-bus, two instruction type, pipelined microprocessor having a control means which orders application of instruction and data addresses to a memory and further interleaves instructions and data on a single bus to achieve maximum efficiency in operation.

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