Method for fabricating an integrated circuit

Details Method for fabricating an integrated circuit Method for fabricating an integrated circuit

1980-10-06

1982-08-24

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

29577C, 29591, 148187, H01L 2122

Patent

active

043453651

ABSTRACT:
This invention pertains to an improved multilevel integrated circuit wherein a single layer of metal or other conductive material is used for interconnection and formation of the conductors and/or gate electrodes of one of the conductor layers. The multilevel integrated circuit of the present invention also includes a thick interlayer insulator which is located between this conductor/interconnect layer and the underlying substrate and lower level conductors to electrically isolate this layer of metal therefrom. The interlayer insulator is not required in the channel region of charge-coupled circuits.

REFERENCES:
patent: 3943543 (1976-03-01), Caywood
patent: 4076557 (1978-02-01), Huang et al.
patent: 4077112 (1978-03-01), Theunissen et al.
patent: 4112575 (1978-09-01), Fu et al.
patent: 4179793 (1979-12-01), Hagiwara
patent: 4193183 (1980-03-01), Klein
patent: 4276099 (1981-06-01), Keen
patent: 4290187 (1981-09-01), Stein
Bertram et al, "A Three-Level Metallization Three-Phase CCD," IEEE Trans. on Electron Devices, vol. ED-21, No. 12, Dec. 1974, pp. 758-767.

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