Two-bit floating point divide circuit with single carry-save add

Details Two-bit floating point divide circuit with single carry-save add Two-bit floating point divide circuit with single carry-save add

1989-04-17

1990-12-18

Malzahn, David H.

Boots, shoes, and leggings

G06F 752

Patent

active

049791427

ABSTRACT:
Apparatus and method for performing floating point divide operations in 2-bit, non-restoring iterations, wherein multiples of the divisor are formed by selective gating of one or more representations of the divisor into a single 3-input adder circuit, to calculate the partial quotients and subsequent partial dividends. The apparatus produces, without the need of separate holding registers, the zero, 1/2, 3/4, 1 and 3/2 multiples of the divisor.

REFERENCES:
patent: 3591787 (1971-07-01), Freiman et al.
patent: 3684879 (1972-08-01), Koehler
patent: 3733477 (1973-05-01), Tate et al.
patent: 3852581 (1974-12-01), Reynard et al.
Jackson et al., "Binary Multiplication & Division Utilizing a Three-Input Adder" IBM Tech. Disclosure Bulletin, vol. 15, No. 7, Dec. 1972, pp. 2263-2268.

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