Mechanism to improved execution of misaligned loads

Details Mechanism to improved execution of misaligned loads Mechanism to improved execution of misaligned loads

1996-09-10

1998-12-29

Lall, Parshotam S.

395376, 395561, 395566, 395380, G06F 930

Patent

active

058549145

ABSTRACT:
A method and apparatus for executing a misaligned load. The method begins with receiving a load request to load data from a first memory location. An entry in a store buffer is tested to determine whether the entry corresponds to the first memory location. The entry is also tested to determine whether the entry corresponds to a second memory location subsequent to the first memory location. The load request is blocked if the entry corresponds to the first memory location or the second memory location. After a store operation for the store buffer entry is executed, the load request may be unblocked. The apparatus is a processor or a computer system comprising a load buffer capable of storing a load request address in response to a load request. The processor includes an incrementing circuit that generates an incremented load request address. The processor also includes a store buffer containing a portion of a store request address. The store buffer includes comparison circuitry that compares the portion of the store request address to the load request and the incremented load request address, and generates a blocking signal if the either of the load request address and the incremented load request correspond to the store request address.

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