Non-volatile semi-conductor memory device with double gate struc

Details Non-volatile semi-conductor memory device with double gate struc Non-volatile semi-conductor memory device with double gate struc

1989-02-27

1989-11-21

Hecker, Stuart N.

Static information storage and retrieval

Floating gate

Particular biasing

357 235, 357 41, 357 45, G11C 1134, H01L 2978, H01L 2702, H01L 2710

Patent

active

048827070

ABSTRACT:
A memory cell structure for a non-volatile semiconductor memory has a semiconductor substrate and first and second diffusion layers having a conductivity type opposite to that of the substrate, formed on the substrate and serve as a source and a drain. The second diffusion layer is coupled through a contact hole to a conductive layer that serves as a bit line. The functions of the first and second diffusion layers as the source and drain are reversed between data write and read modes. A floating gate and a control gate are insulatively provided on the substrate in parallel to each other. In either the data write mode or data read mode, the first and second diffusion layer are applied with a bias voltage while the control gate is initially applied with a ground voltage. A memory cell is selected by dropping the bias voltage on the second diffusion layer. The potential on the first diffusion layer is kept unchanged to constantly maintain the initially-applied bias voltage even when the memory cell is selected, so that the first diffusion layer is permitted to be coupled to the common wiring line together with the corresponding first diffusion layers of the other memory cells.

REFERENCES:
patent: 4385308 (1983-05-01), Uchida
patent: 4558339 (1985-12-01), Angle
patent: 4589009 (1986-05-01), Motamedi
patent: 4665418 (1987-05-01), Mizutani
patent: 4698787 (1987-10-01), Mukherjee et al.
patent: 4754320 (1988-07-01), Mizutani et al.
patent: 4766473 (1988-08-01), Kuo
patent: 4783766 (1988-11-01), Samachisa et al.
IEEE Transactions on Electron Devices, vol. ED-34, No. 6, Jun. 1987, "Characteristics of a New EPROM Cell Structure with a Sidewall Floating Gate".
Y. Mizutani and K. Makita, in IEDM Tech. Dig., pp. 635-638, 1985.

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