Patent
1997-10-30
1998-12-29
Barry, Esq., Lance Leonard
395292, G06F 1300
Patent
active
058549064
ABSTRACT:
A method and apparatus for packet-switched flow control of transaction requests that maximizes resource utilization and throughput, and minimizes latency. An interconnect system controller provides dedicated transaction request queues for master interfaces and controls the forwarding of transactions to slave interfaces. The master interface keeps track of the number of requests in the dedicated queue in the system controller, and the system controller keeps track of the number of requests in each slave interface queue. An acknowledgement from a downstream queue indicates to the sender that there is space in it for another transaction. Accelerated processing of transaction requests from a processor to a slave device on its local address bus is achieved by immediately forwarding the request to the slave device while determining the validity of the request for that slave, including whether the slave's input queue can accept it. If the validity of the criteria are met and the request is indeed intended for the local slave device, it is immediately validated for processing by the slave. This obviates the need for the system controller to reassert the address bus and send the request on to the slave, resulting in savings of several clock cycles per request from a processor to a slave device on its local address bus. In uniprocessor systems, this savings is realized on virtually every slave request, since all slaves in a uniprocessor system are of necessity on the local address bus for the single processor.
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Barry, Esq. Lance Leonard
Kivlin B. Noel
Sun Microsystems Inc.
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