Excavating
Patent
1998-01-20
1998-12-29
Nguyen, Hoa T.
Excavating
371 275, 371 276, 371 211, G01K 3128
Patent
active
058548017
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
This invention relates to a test pattern generation apparatus and method for generating a test pattern to test a synchronous dynamic random access memory (hereinafter referred to as "SDRAM").
BACKGROUND ART
In general, a semiconductor test system has to test various types of semiconductor devices by generating test patterns. A higher operation speed is ever desired in the recent semiconductor devices to be tested, and as a result, an SDRAM has become more common in the market.
An SDRAM has an increased operation speed by continuously accessing a block of memory cells by itself unlike the conventional DRAM which is accessed cell by cell. An SDRAM has a special architecture to speed up the continuous access, enabling a read/write rate of 100 M byte/second or higher. To increase the continuous access, the read and write process in the SDRAM is performed by a burst method. The burst method is a process in which the data for the same row address is read and written as a unit of block such as 2, 4 or 8 words. In such an operation, only the start address of a block is given, and the subsequent address thereafter is incremented within the SDRAM by itself, thereby achieving the high-speed performance.
There are two methods for incrementing the address after the start address for the continuous address block in the SDRAM, i.e., wrap types, one is a sequential type and the other is an interleave type. FIG. 8 shows an example of address sequence in the SDRAM. The example of FIG. 8 has a burst length of 8 words. When the start address for the continuous access block is given, data is transferred continuously to the block. The order of the transfer is predetermined by specifications of the SDRAM, and as shown in FIG. 8, there is a difference between the sequential wrap type and the interleave wrap type.
FIG. 7 is an example of address allocations in the wrap address. A part of the column address of the SDRAM is assigned as a wrap address for the burst operation. FIG. 6 shows an example of pattern generation in the conventional semiconductor test system. This drawing shows the relationship between the address of the SDRAM that is a device 20 to be tested and the address from a pattern generator 10. In this example, the address X0-X11 of the pattern generator is allocated to the row address of the SDRAM. The address Y0-Y2 of the pattern generator is allocated to the wrap address of the SDRAM. For the rest of column address of the SDRAM, the address Z0-Z5 of the pattern generator is assigned. The allocations of address generation are necessary in such a way that correspond to the continuous address in the device to be tested so as to prepare for the case where a failure has occurred in the device to be tested and quality analysis must be performed. Hence, the test pattern will be generated based on a mathematical function of the pattern generator.
In the pattern generator of the conventional semiconductor test system, for generating a complex pattern such as the sequential type address or the interleave type address of SDRAM for testing the SDRAM, the standard operational ability in the pattern generator cannot cover the complexity of the pattern generation. Thus, for generating such patterns, it is necessary to pre-install a complex pattern program produced by a mathematic process. In addition to the complexity, there is a problem that a start column address for the burst operation cannot be set algorithmically.
The present invention has been made to overcome the above problems in the conventional technology and provides a test pattern generation apparatus for SDRAM that can easily generate test patterns for testing the SDRAM by adding a specific wrap address conversion circuit as well as a test pattern generation method for SDRAM by converting the address from the pattern generator to the wrap address.
DISCLOSURE OF THE INVENTION
According to the first embodiment of the present invention, a test pattern generation apparatus is provided to effectively test an SDRAM. The pattern generation apparatus
REFERENCES:
patent: 4754215 (1988-06-01), Kawai
patent: 4862460 (1989-08-01), Yamaguchi
patent: 5214654 (1993-05-01), Oosaura
patent: 5341492 (1994-08-01), Sakata
patent: 5739778 (1998-04-01), Tae
Hara Koji
Yamada Osamu
Advantest Corp.
Nguyen Hoa T.
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