Method of and apparatus for testing semiconductor memory

Details Method of and apparatus for testing semiconductor memory Method of and apparatus for testing semiconductor memory

1997-05-21

1998-12-29

Canney, Vincent P.

Excavating

G06F 1100

Patent

active

058547967

ABSTRACT:
A failure analysis memory for storing failure information representative of a test result of a semiconductor memory under test is divided into a plurality of blocks with compacted addresses, and a compaction memory having areas corresponding respectively to the blocks of the failure analysis memory is prepared. Data indicative of a failure cell in any one of the blocks of the failure analysis memory is written in an area of the compaction memory which corresponds to the any one of the blocks. Minimum and maximum addresses of addresses at which failure cells are present in the blocks are determined, and failure data is read from the failure analysis memory in a range between the minimum and maximum addresses of each of the blocks, which correspond to the areas of the compaction memory which store the data indicative of a failure cell.

REFERENCES:
patent: 5173906 (1992-12-01), Dreubelbis et al.

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