Memory capacity test method and computer system

Details Memory capacity test method and computer system Memory capacity test method and computer system

1997-02-14

1998-12-29

Tu, Trinh L.

Excavating

365201, G11C 2900

Patent

active

058547959

ABSTRACT:
A memory capacity test method capable of confirming the memory capacity of an actually mounted memory in a short time in a memory system which mounts a memory only on a portion of a memory space. The method writes first data to a check address which is an n-th power of two, and then second data to the address 0, where the second data differs from the first data, and decides that the memory is not mounted on the check address if the data read from the check address disagrees with the first data. This is based on the fact that the check address actually points the address 0 when the memory is not mounted on the check address of the nth power of two, and hence the second data is written over the first data on the address 0 in that case.

REFERENCES:
patent: 4479214 (1984-10-01), Ryan
patent: 4535455 (1985-08-01), Peterson
patent: 4943910 (1990-07-01), Nakamura
patent: 5388104 (1995-02-01), Shirotori et al.

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