Super-compact hardware architecture for IDCT computation

Details Super-compact hardware architecture for IDCT computation Super-compact hardware architecture for IDCT computation

1996-05-07

1998-12-29

Moise, Emmanuel L.

Boots, shoes, and leggings

382250, G06F 1714

Patent

active

058547576

ABSTRACT:
An Inverse Discrete Cosine Transform processor employs symmetry and reusable elements to use a fewer number of gates while maintaining processing speed at an acceptable level. Even and odd sums are generated simultaneously by even and odd sum generators. A butterfly operation is then performed on the on the even and odd sums to produce pairs of transformed elements simultaneously. For an 8.times.8 block, the even and odd sum generators can be designed to a generate four pairs of even and odd sums sequentially. This design allows a single row or column of eight elements to be processed in 4 clock cycles. A horizontal transformation on all eight rows of the block can be performed in 32 cycles. A vertical transformation can then be performed by storing the transformed rows in a second memory, reading out columns from the second memory, and using the same hardware to generate the sums and perform the butterfly operation on the columns. An entire two-dimensional transformation can be performed in only 64 clock cycles.

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