Method of making trench DRAM cell with stacked capacitor and bur

Details Method of making trench DRAM cell with stacked capacitor and bur Method of making trench DRAM cell with stacked capacitor and bur

1989-07-25

1990-12-18

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 38, 437 47, 437 60, 437162, 437203, 437228, 437919, 357 236, H01L 21265

Patent

active

049786342

ABSTRACT:
The described embodiments of the present invention provide DRAM cells, structures and manufaturing methods. In a first embodiment, a DRAM cell with a trench capacitor having a first plate formed as a diffusion on the outside surface of a trench formed in the substrate and a second plate having a conductive region formed inside the trench is fabricated. The transfer transistor is formed using a field plate isolation structure which includes a self-aligned moat area for the transfer transistor. The moat area slightly overlaps the capacitor area and allows for increased misalignment tolerance thus foregoing the requirement for misalignment tolerances built into the layout of the DRAM cell. The field plate itself is etched so that it has sloped sidewalls to avoid the formation of conductive filaments from subsequent conductive layers formed on the integrated circuit. The use of a self-aligned bitline contact between two memory cells allows for the elimination of alignment tolerances between the bitline contact and the gates of the transfer transistors of the memory cells.

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Nakajima et al., "An Isolation-Merged Vertical Capacitor Cell for Large Capacity DRAM", IEDM 1984, pp. 240-243.

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