MOS Buffer circuit

Details MOS Buffer circuit MOS Buffer circuit

1977-07-25

1978-07-25

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307205, 307304, 307DIG1, 307DIG5, H03K 3353, H03K 1908, H03K 1940

Patent

active

041031890

ABSTRACT:
An MOS buffer circuit which may be employed as part of a electrically programmable read-only memory or other MOS integrated circuit is described. The buffer may be "powered down" when the memory is in a standby mode. Low threshold (zero threshold) voltage devices are employed in the circuit along with depletion mode transistors and enhancement mode transistors in a manner which permits the buffer to be readily powered down.

REFERENCES:
patent: 3700981 (1972-10-01), Masuhara et al.
patent: 3778784 (1973-12-01), Karp et al.
patent: 3824564 (1974-07-01), Wegener
patent: 3895360 (1975-07-01), Cricchi et al.
patent: 3938108 (1976-02-01), Salsbury et al.
patent: 3940747 (1976-02-01), Kuo et al.
patent: 3946369 (1976-03-01), Pashley
patent: 3959781 (1976-05-01), Mehta et al.
patent: 3969633 (1976-07-01), Paluck et al.
patent: 4021656 (1977-05-01), Caudel et al.
patent: 4042839 (1977-08-01), Araki
Dansky, "Multiple Threshold IGFET Ternary Circuits," IBM Tech. Discl. Bull.; vol. 17, No. 5, pp. 1356-1357, 10/1974.
Hayashi et al., "Design of ED-MOS Buffer," Electronics and Communications in Japan, (pub.), vol. 55-c, No. 10; 10/1972; pp. 107-114.
Kuo et al., "16K RAM Built With Proven Process May Offer High Start-Up Reliability," Electronics, (Pub.); pp. 81-86; 5/13/1976.

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