Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1976-09-20
1978-07-25
Anagnos, Larry N.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
58 23A, 58 23BA, 307200B, 307247A, 307279, 307296R, 328 48, H03K 1722, H03K 1720, H03K 1760, H03K 2132
Patent
active
041031873
ABSTRACT:
A semiconductor integrated power-on reset circuit that is formed on the same monolithic substrate as the circuitry that same is adapted to reset in order to obtain higher component density on the monolithic substrate is provided. The circuitry on the monolithic substrate defines a predetermined parasitic capacitance and includes a voltage supply for selectively applying a supply voltage to the circuitry to operate the circuitry at the supply voltage after a first predetermined interval of time. The power-on reset circuit is disposed intermediate the voltage supply and the circuitry and includes at least one pair of complementary coupled P-channel and N-channel MOS transistors, coupled to define an output terminal having the predetermined parasitic capacitance thereat. The output terminal of the reset circuit is coupled to the circuitry and applies a reset signal to the circuitry after the circuitry is energized to the supply voltage in response to the supply voltage being selectively applied to the reset circuit.
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Lohman, "Applications of MOSFETs in Microelectronics"; SCP and Solid-State Technology; pp. 23-29, 3/1966.
Hanchett, "Turn-On Reset Pulse Circuits"; RCA Technical Notes; TN No. 927; 4 pp. 3/28/73.
Suzuki, et al., "Clocked CMOS Calculator Circuitry"; 1973 IEEE Int'l Solid-State Circuits Conference; 2/14/73, pp. 58-59, (Digest of Technical Papers).
Anagnos Larry N.
Kabushiki Kaisha Suwa Seikosha
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