Process for manufacturing isolated semi conductor components in

Details Process for manufacturing isolated semi conductor components in Process for manufacturing isolated semi conductor components in

1984-06-18

1987-07-14

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29578, 29580, 29576E, 148175, 148DIG11, 357 49, H01L 2176

Patent

active

046793097

ABSTRACT:
A process for manufacturing isolated semi conductor components in a semi conductor wafer of the type used in bipolar technology. In this process, polycrystalline silicon is deposited in a recess in a silicon substrate whose walls are insulated by a silicon nitride layer except for an opening formed in this nitride layer at the bottom of said recess. Then, the polycrystalline silicon is re-epitaxied so as to become monocrystalline silicon by thermal heating from the "nucleus" formed by the underlying silicon in said opening.

REFERENCES:
patent: 4494303 (1985-01-01), Celler et al.
Yu, "Fabrication of Planar Arrays of Semiconductor Chips by Epitaxial Growth", IBM Tech. Discl. Bulletin, 7, (11), 4/65.
Patents Abstracts of Japan, vol. 5, No. 159(E-77) (831), Jul. 15, 1981 & JP-Ap-56 87 339 (Nippon Denki K.K.) (15-0701981).
IBM Technical Disclosure Bulletin, vol. 24, No. 7B, Dec. 1981, pp. 3684-3688, New York (USA); H. H. Hansen et al.: "Improved Device Packing Density", p. 368, paragraph 4-p. 3688, paragraph 1; figures 5-9.
International Electron Devices Meeting, Dec. 13-15, 1982, pp. 224-227, IEEE New York (USA); K. Y. Chiu et al.: "The Swami-A Defe-t Free and Near-Zero Bird's-Beak Local Oxidation Process and its Application in VLSI Technology", Figures 1-2.
International Electron Devices Meeting, Dec. 13-15, 1982, pp. 241-244, IEEE, New York (USA); N. Endo et al.: "Novel Device Isolation Technology with Selective Epitaxial Growth", Figure 1.

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