Non-volatile memory

Details Non-volatile memory Non-volatile memory

1990-01-19

1991-08-27

Moffitt, James W.

Static information storage and retrieval

Floating gate

Particular biasing

36518905, G11C 1140

Patent

active

050439413

ABSTRACT:
A non-volatile memory provides a signal hold circuit which uses a FAMOS instead of an input transistor of a ratiod inverting amplifier and outputs a change in a threshold value of the FAMOS, for the purpose of reducing the number of elements of the signal hold circuit. FAMOSs for programming and latching are provided respectively, and the FAMOSs are interconnected to each other at their floating gate electrodes to isolate the signal hold circuit and a program circuit and hence prevent a DC current path from being formed between those two circuits, for the purpose of miniaturization of a memory cell.

REFERENCES:
patent: 4030081 (1977-06-01), Horninger
patent: 4573144 (1986-02-01), Countryman, Jr.
patent: 4788663 (1988-11-01), Tanaka et al.
patent: 4829203 (1989-05-01), Ashmore, Jr.
Sau-Ching Wong et al., "Novel Circuit Techniques for Zero-Power 25-ns CMOS Erasable Programmable Logic Devices (EPLD's)", Oct. 5, 1986, IEEE Journal of Solid-State Circuits, vol. SC-21, pp. 766.varies.774.
1985 IEEE International Solid-State Circuits Conf., Session XIII: Nonvolatile Memories, "THPM 13.2: A 100ns 256K CMOS EPROM", H. Gaw et al., pp. 164-165, attached FIGS. 4, 5, Table 1 (pp. 333-334).

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