Node controller for a local area network

Details Node controller for a local area network Node controller for a local area network

1990-10-17

1991-08-27

Shaw, Gareth D.

Boots, shoes, and leggings

36494062, 36494063, 36494064, 34082503, 34083505, 370 61, 370 8515, 370 855, H04L 1228, H04L 1240, H04L 1242

Patent

active

050439383

ABSTRACT:
A controller has a node interface logic (40), a ring bus interface logic (42), a set of input pins (44) and a set of output pins (45). A common logic (58) is connected to the node interface logic (40) and to the ring bus interface logic (42). The common logic includes an output FIFO buffer (32) connected to an output link interface (37) and an input FIFO buffer (34) connected to an input link interface (36). A mode select pin (43) is provided for selecting a node controller mode of operation and a ring controller mode of operation. The node interface (40) responds to assertion of the selection pin (43) to activate the pins (44, 45) with respect to the node interface (40). The ring bus interface (42) responds to deassertion of the select pin (43) to activate the pins (44, 45) with respect to the ring bus interface (42).

REFERENCES:
patent: 4768190 (1988-08-01), Giancarlo
patent: 4769813 (1988-09-01), Lenart
patent: 4803485 (1989-02-01), Rypinsky
patent: 4857709 (1989-07-01), Matsumoto et al.
Ralston, Anthony and Edwin D. Reilly, Jr., Memory-Mapped I/O, Encyclopedia of Computer Science and Engineering, p. 967 (2nd Ed. 1983).

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