Microcomputer computer system having plural programmable timers

Details Microcomputer computer system having plural programmable timers Microcomputer computer system having plural programmable timers

1994-07-19

1996-03-05

Kriess, Kevin A.

Boots, shoes, and leggings

364270, 3642702, 3642703, 3642706, 364DIG1, G06F 104

Patent

active

054974810

ABSTRACT:
A microcomputer system includes: a plurality of DMA data transfer paths for use with a random access memory, at least one of the data transfer paths being set up by a central processing unit under control of a program stored in a read only memory; a plurality of memory locations of the random access memory assigned to the plurality of DMA data transfer paths respectively, each memory location storing time setting data; a timing signal generating unit for outputting a timing signal at predetermined intervals; a DMA control unit for reading out each time setting value from first memory locations through first DMA data transfer paths respectively in synchronism with the timing signal; a detecting unit for detecting whether the time setting value is equal to zero; a plurality of subtraction registers for decrementing the time setting value by one when the time setting value is detected to be unequal to zero; and a writing unit for writing the decremented time setting value into corresponding one of the first memory locations through corresponding one of the first DMA data transfer paths in conjunction with the DMA control unit.

REFERENCES:
patent: 4688166 (1987-08-01), Schneider
patent: 4716523 (1987-12-01), Burrus et al.
patent: 4782439 (1988-11-01), Borkar et al.
Intel Data Sheets, "82C54 CHMOS Programmable Interval Timer", Oct. 1987, pp. 2-46-2-63.

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