Oxide-isolated source/drain transistor

Details Oxide-isolated source/drain transistor Oxide-isolated source/drain transistor

1988-08-25

1991-08-27

James, Andrew J.

357 42, 357 59, 357 49, 357 15, H01L 2978, H01L 2702, H01L 2904, H01L 2712

Patent

active

050437780

ABSTRACT:
A MOS bulk device having source/drain-contact regions 36 which are almost completely isolated by a dielectric 35. These "source/drain" regions 36 formed by using a silicon etch to form a recess, limiting the etched recess with oxide, and backfilling with polysilicon. A short isotropic oxide etch, followed by a polysilicon filament deposition, then makes contact between the oxide-isolated source/drain-contact regions 36 and the channel region 33 of the active device. Outdiffusion through the small area of this contact will form small diffusioins 44 in silicon, which act as the electrically effective source/drain regions. Use of sidewall nitride filaments 30 on the gate permits the silicon etch step to be self-aligned.

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patent: 4587710 (1986-05-01), Tsao
patent: 4613885 (1986-09-01), Haken
Anantha et al., "IC Incorporating CMOS Devices" IBM Tech. Discl. Bulletin, vol. 16, No. 10, Mar. 1974, p. 3245.
Shinchi et al., "The Buried Oxide MOSFET" IEEE Transactions on Electron Devices, Oct. 1976, pp. 1190-1191.

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