Power FETS with improved high voltage performance

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357 232, 357 16, 357 17, H01L 2980, H01L 29161, H01L 3300, H01L 2920

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active

050437771

ABSTRACT:
An undoped surface layer over and lattice matched to the n-channel layer between the gate contact and the spaced apart source and drain n+ regions in power FETs made of group III-V compounds minimizes surface effects that preclude such devices from operating efficiently at high voltages, and improves reliability. The undoped surface layer may be grown on the n-channel layer before the layer forming the n+ regions, or where the n+ regions can be formed in the undoped surface layer. The invention is especially suitable for GaAs MESFETs and HEMTs.

REFERENCES:
patent: 4641161 (1987-02-01), Kim et al.
patent: 4916498 (1990-04-01), Berenz
H. M. Macksey; "GaAs Power FET's Having the Gate Recess Narrower Than the Gate", IEEE Electron Device Letters, vol. EDL-7; No. 2, Feb. 1986, pp. 69-70.
Stephen R. Blight et al., IEEE Transactions on Electronic Devices; vol. ED-33 No. 10, Oct. 1986, pp. 1447-1453.
H. M. Macksey et al., S-band GaAs Power FET with a Semi-Insulating Gate; Inst. Phys. Conf. Ser. No. 65: Chapt. 5 Paper presented at Int. Symp. GaAs and Related Compounds; Albugquerque, 1982, 371-378.
Masashi Ozeki et al., Surface Analysis in GaAs MESFETs by g.sub.m frequency dispersion measurement; Inst. Phys. Conf. Ser. No. 63, Chapt. 7 Paper presented at Int. Symp. GaAs and Related Compounds, Japan, 1981; pp. 323-328.

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