Data addressable memory architecture and method of forming a dat

Boots – shoes – and leggings

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395400, 364DIG1, 365 49, 36523005, G06F 1300, G06F 1202

Patent

active

051828022

ABSTRACT:
A data addressable memory (DAM) architecture includes a set of log, twist and linked list memories each having control, address and data ports. The log, twist and linked list memories also define respective arrays of log, twist, and linked list memory locations capale of being enabled and controlled via the control ports, identified via the address ports, and written into and read from via the data ports. The DAM architecture also includes a control arrangement which connnects control, address and data buses with the control, address and data ports of the log, twisted and linked list memories. The log, twist and linked list memory locations of the respective memories are controlled, identified, written and read via the respective control, address and data ports thereof such that all data values can be stored in respective memory locations of the RAM architecture without over-writing all duplicates thereof and all data values can be recovered from the respective memory locations of the DAM architecure without searching all memory locations.

REFERENCES:
patent: 4622653 (1986-11-01), McElroy
patent: 4755974 (1988-07-01), Yamada et al.
patent: 5122984 (1992-06-01), Strehler

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