Excavating
Patent
1995-06-01
1996-03-05
Canney, Vincent P.
Excavating
271 251, 271 26, G06F 1110
Patent
active
054973813
ABSTRACT:
Defects in the manufacturing of IC devices are analyzed by testing the devices for defects, generating a serial digital data bitstream upon which the test result for each device is encoded in succession, and operating upon the data bitstream to analyze the device defects. This allows for the use of rapid and reliable digital signal processing techniques to perform the analysis. The types of analyses that can be performed include the determination of non-random yields to distinguish random from systematic defects, comparisons with signature defect patterns that correspond to various systematic faults, and yield predictions for other circuits manufactured with a similar process but having a different critical circuit area. An improved windowing technique is used to determine non-random defects, in which normalized defect counts are obtained and compared for various window sizes. Multiple functional and parametric tests for each device can be accommodated in several ways, including the assignment of additional data bits in the bitstream to the additional tests. The defect analysis can be performed in real-time on one batch while the next batch is being processed, with the results of the analysis used to correct the manufacturing process if systematic defects are identified. An improved method is also described for calculating the non-random yield loss factor Y.sub.o, which can be used in yield models for yield prediction purposes.
REFERENCES:
Cheek and O'Donoghue, "Yield Modeling in a DFM Environment: A Bibliography", International Semiconductor Manufacturing Science Symposium, San Francisco, 1993.
Kiberian and Strojwas, "Using Spatial Information To Analyze Correlations Between Test Structure Data", IEEE Transactions on Semiconductor Manufacturing, vol. 4, No. 3, Aug. 1991.
Stapper et al., "Integrated Circuit Yield Statistics", Proceedings of the IEEE, vol. 71, No. 4, Apr. 1983.
Riodan and Vasques, "Statistical Bin Limits: Containing Factory Excursions Near the Source", 18th Annual Reliability Testing Institute, University of Arizona, May 1992.
Hoel, Elementary Statistics, 2d, Ed., John Wiley & Sons, 1966, pp. 258-260 and 284-287.
Oppenheim and Schafer, Digital Signal Processing, Prentice Hall, 1975.
Oppenheim & Schaffer, Digital Signal Processing, Prentice-Hall, 1975, pp. 195-197, and 137-239.
Stapper et al., "Integrated Circuit Yield Statistics", Proceedings of the IEEE, vol. 71, No. 4, Apr., 1983, pp. 453-470.
Riordan and Vasquez, "Statistical Bin Limits: Containing Factory Excursions Near and the Source", 18th Annual Reliability Testing Institute, University of Arizona, May, 1992, pp. 1-14.
Hoel, Elementary Statistics, 2d Ed., John Wiley & Sons, 1966, pp. 257-260 and 284-287.
Cheek and O'Donoghue, "Yield Models in a Design for Manufacturability Environment: A Bibliography", International Semiconductor Manufacturing Science Symposium, San Francisco, 1993, pp. 133-135.
Kiberian and Strojwas, "Using Spatial Information to Analyze Correlations Between Test Structure Data", IEEE Transactions on Semiconductor Manufacturing, vol. 4, No. 3, Aug., 1991, pp. 219-225.
Cheek Gary C.
O'Donoghue Geoffrey P.
Analog Devices Inc.
Canney Vincent P.
LandOfFree
Bitstream defect analysis method for integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Bitstream defect analysis method for integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bitstream defect analysis method for integrated circuits will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1417264