Boots – shoes – and leggings
Patent
1994-10-21
1996-03-05
Teska, Kevin J.
Boots, shoes, and leggings
364488, 364490, H03B 714
Patent
active
054973376
ABSTRACT:
A method of designing a high Q inductor for implementation in multiple metalization levels in conventional integrated circuit technology uses a software assisted iterative technique to achieve a design Q factor. The inductor turns utilize the multiple metalization levels to reduce inductor resistance.
REFERENCES:
patent: 3598977 (1971-08-01), Clemmens
patent: 3622762 (1971-11-01), Dyer et al.
patent: 4071903 (1978-01-01), Head et al.
patent: 4351983 (1982-09-01), Crouse et al.
patent: 4542356 (1985-09-01), Nakazawa et al.
patent: 4672669 (1987-06-01), DesBlanche et al.
patent: 4677671 (1987-06-01), Galand et al.
patent: 4764966 (1988-08-01), Einkauf et al.
patent: 4841574 (1989-06-01), Pham et al.
patent: 4907277 (1990-03-01), Callens et al.
patent: 4924508 (1990-05-01), Creyp et al.
patent: 4933860 (1990-06-01), Liu
patent: 4933957 (1990-06-01), Bottau et al.
patent: 4981838 (1991-01-01), Whitehead
patent: 5001758 (1991-03-01), Galand et al.
patent: 5007092 (1991-04-01), Galand et al.
patent: 5010495 (1991-04-01), Willetts
patent: 5031218 (1991-07-01), Galand et al.
patent: 5073941 (1991-12-01), Locke
patent: 5113011 (1992-05-01), Witzeman et al.
patent: 5124675 (1992-06-01), Komazaki et al.
patent: 5133011 (1992-07-01), McKiel, Jr.
patent: 5142583 (1992-08-01), Galand et al.
patent: 5230037 (1993-07-01), Giustiniani et al.
patent: 5231669 (1993-07-01), Galand et al.
patent: 5241245 (1993-08-01), Barnes et al.
patent: 5276398 (1994-01-01), Withers et al.
patent: 5285191 (1994-02-01), Reeb
patent: 5293451 (1994-03-01), Brown et al.
patent: 5293584 (1994-03-01), Brown et al.
patent: 5297053 (1994-03-01), Pease et al.
patent: 5304967 (1994-04-01), Hayashi
patent: 5313398 (1994-05-01), Rohrer et al.
"Three-Dimensional Inductance Computations with Partial Element Equivalent Circuits", by Pierce Brennan, Norman Raver and Albert Ruehli, IBM J. Res. Develop., vol. 23, No. 6, Nov. 1979, 661-668.
"Frequency-Dependent Inductance and Resistance Calculation for Three-Dimensional Structure in High-Speed Interconnect Systems", by A. C. Cangellaries, J. L. Prince and L. Vakanas, IEEE Trans. Compon. Hybrids Manuf. Tech. vol. 13, No. 1, Mar. 1990, 398-403.
"Capacitance Calculation of IC Packages Using the Finite Element Method and Planes of Symmetry", by Tai-Yu Chou and Zoltan Cendes, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, No. 9, Sep. 1994, 1159-1166.
"Inductance Calculations in a Complex Integrated Circuit Environment", by A. E. Ruehli, IBM J. Res. Develop., Sep. 1972, 470-481.
"Equivalent Circuit Models for Three-Dimensional Multiconductor Systems", by A. E. Ruehli, IEEE Trans. on Microwave Theory and Techniques, vol. MTT-22, No. 3, Mar. 1974, 216-221.
"Efficient Capacitance Calculations for Three-Dimensional Multiconductor Systems", by A. E. Ruehli and P. A. Brennan, IEEE Trans. on Microwave Theory and Techniques, vol. MTT-21, No. 2, Feb. 1973, 76-82.
"Inductance of Nonstraight Conductors Close to a Ground Return Plane", by A. E. Ruehli, N. Kulasza and J. Pivnichny, IEEE Trans. on Microwave Theory and Techniques, Aug. 1975, 706-708.
"A Package Analysis Tool Based on a Method of Moments Surface Formulation", by S. Ponnapalli, A. Deutsch and R. Bertin, IEEE Trans. on Components, Hybrids and Manufacturing Technology, vol. 16, No. 8, Dec. 1993, 884-892.
"IDEAS-An Integrated Design Automation System", by Mehmood et al., 1987 International Conference on Computer Design: VLSI in Computers and Processors, Oct. 5-8, 1987, pp. 407-412.
IBM Technical Disclosure Bulletin, vol. 32, No. 6B, Nov. 1989, pp. 310-317, "Programmable Substrate Inductor", by A. A. Mello.
Ewen John F.
Ponnapalli Saila
Soyuer Mehmet
Frejd Russell W.
International Business Machines - Corporation
Teska Kevin J.
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