Semiconductor integrated circuit device fabrication method and i

Details Semiconductor integrated circuit device fabrication method and i Semiconductor integrated circuit device fabrication method and i

1994-06-08

1996-03-05

Envall, Roy

Boots, shoes, and leggings

395900, 395904, 364552, G06F 1900, G06F 1760

Patent

active

054973317

ABSTRACT:
A semiconductor integrated circuit device fabrication technique improves the accuracy of element qualities by considering the influence of interaction of element quality parameters in the quality control of semiconductor fabrication processes and also by improving the product yield estimation accuracy so that the production efficiency can be improved. An initial value of a membership function is first set and then a plurality of element quality parameters and a combined quality parameter are expressed by membership functions in fuzzy control in a semiconductor fabrication apparatus for automating a fabrication method by connecting a computer with various measuring instruments and various processors by communication devices. Moreover, the combined quality parameters are fuzzy-inferred from the element quality parameters using these membership functions, inference rules are adjusted by data of the actual processes, the membership functions of the obtained element quality parameters are converted into an element quality control standard, and the semiconductor integrated circuit device fabrication processes are controlled in accordance with the standard.

REFERENCES:
patent: 5388186 (1995-02-01), Bose
patent: 5392361 (1995-02-01), Imaizumi et al.
patent: 5410495 (1995-04-01), Ramamurthi
Shoichiro Kinoshita, et al., "Achieving an Automated 8-inch Line for 4-Mbit Memory at Yasu Works of IBM Japan Ltd.--Using Feedback Control in the Exposure Process and Failure Analysis Software", Nikkei Microdevices, Jun., 1991, pp. 87-95 (full translation).

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