Differential amplifier circuit having a bias circuit with a diff

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Nonlinear amplifying circuit

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Details

327541, 327543, 330253, 330261, H03K 1716, H03F 345

Patent

active

054971209

ABSTRACT:
A differential amplifier circuit is obtained in which an operating power source voltage is suppressed to a minimum necessary level. The differential amplifier circuit includes a bias circuit having a differential amplifier with NMOS transistors (11A, 11B, 12A and 12B) and PMOS transistors (13A and 13B). Sources of NMOS transistors (11A)and (11B) are commonly grounded. A bias voltage (VB1) is supplied to gates of the NMOS transistors (11A) and (11B). Drains of the NMOS transistors (11A) and (11B) are connected to sources of NMOS transistors (12A) and (12B), respectively. A gate and a drain of the NMOS transistor (12A) are short-circuited to each other with the drain connected to a drain of a PMOS transistor (13A). A bias voltage (VB4) is applied to a gate of the NMOS transistor (12B). A drain of the NMOS transistor (12B) is connected to a drain of the PMOS transistor (13B) whose gate and drain are shared by each other. Gates of the PMOS transistors (13A) and (13B) are connected to a bias terminal (72) while sources of the PMOS transistors (13A) and (13B) are commonly connected to a power source. The bias terminal (72) is connected to an input bias terminal of a differential amplifier.

REFERENCES:
patent: 5061862 (1991-10-01), Tamagawa
patent: 5065046 (1991-11-01), Mok
patent: 5124580 (1992-06-01), Matthews et al.
patent: 5187448 (1993-02-01), Brooks et al.
patent: 5202645 (1993-04-01), Phan et al.
patent: 5367201 (1974-11-01), Hedberg

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