Process compensated input switching threshold of a CMOS receiver

Details Process compensated input switching threshold of a CMOS receiver Process compensated input switching threshold of a CMOS receiver

1990-12-20

1992-05-05

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307443, H03K 19017, H03K 5153, H03K 19092, H03K 19094

Patent

active

051110814

ABSTRACT:
Described is a circuit arrangement which controls the range of input voltages at which the output of a CMOS inverter switches. The circuit arrangement includes a plurality of FET devices disposed in parallel with one of the CMOS inverter devices. The FET devices are selectively switched to adjust the (W/L) ratio of said one of the CMOS inverter devices. Therefore, as the switching threshold of the inverter changes due to tempeature, process variations, etc., the (W/L) ratio of the said one of the CMOS inverter devices is adjusted to compensate for the changes.

REFERENCES:
patent: 4794283 (1988-12-01), Allan et al.
patent: 4845388 (1989-07-01), Amatangelo
patent: 4855623 (1989-08-01), Flaherty
patent: 4975599 (1990-12-01), Petrovick, Jr.

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