Power reduction circuit for programmable logic device

Details Power reduction circuit for programmable logic device Power reduction circuit for programmable logic device

1990-06-29

1992-05-05

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307494, 3072963, 36518908, H03K 19177

Patent

active

051110792

ABSTRACT:
According to the present invention, during programming of a programmable logic device, programming information corresponding to an input signal is loaded into a shift register. This input information is compared with programming information corresponding to a second, complementary input signal to determine if the two signals are used by the programmable logic device. If the two inputs are not used, a bit is stored in a memory cell indicating such nonuse. An input buffer is disabled when the bit in the memory cell indicates the complementary signals corresponding to that input buffer are not used.

REFERENCES:
patent: 4761570 (1988-08-01), Williams
patent: 4906862 (1990-03-01), Itano et al.
patent: 4940909 (1990-07-01), Mulder et al.
patent: 4963769 (1990-10-01), Hiltpold et al.
patent: 4992679 (1991-02-01), Takata et al.
patent: 5012135 (1991-04-01), Kaplinsky

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