Process for manufacturing a DRAM cell

Details Process for manufacturing a DRAM cell Process for manufacturing a DRAM cell

1990-11-28

1991-08-27

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 47, 437 48, 437 49, 437 60, 437191, 437919, 437981, H01L 2170

Patent

active

050432982

ABSTRACT:
When a semiconductor device having a multi-layered contact is fabaricated, the gate electrode is covered with a thick insulator film. A polycrystalline silicon film is formed in a state in which at least the gate electrode in the contact forming area is covered with a first oxidization-proof insulator film. An inter-layer insulator film is then formed in a state in which at least part of the polycrystalline silicon film is covered with a second oxidization-proof insulator film. A first contact hole is formed using the polycrystalline silicon film as an etching stopper, and the polycrystalline silicon film is then oxidized. Furthermore, a second contact hole is formed in the inter-layer insulator film on the upper surface of the second oxidization-proof insulator film using as the etching stopper the polycrystalline silicon film underlying the second oxidization-proof insulator film. Since the polycrystalline silicon film is formed under the inter-layer insulator film in the second contact forming area so as to cover the gate electrode, it acts as a stopper when the second contact is formed to thereby prevent a short circuit with the gate electrode even if there is no distance between the gate electrode and the second contact.

REFERENCES:
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patent: 4069067 (1978-01-01), Ichinohe
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patent: 4455737 (1984-06-01), Godejahn
patent: 4686000 (1987-08-01), Heath
patent: 4694565 (1987-09-01), Custode
patent: 4697328 (1987-10-01), Custode
patent: 4855801 (1989-08-01), Kuesters
Extended Abstracts, (The 35th Spring Meeting, 1988), The Japanese Society of Applied Physics and Related Societies, M. Kubota et al., 28p-V-4, 1988.

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