Fishing – trapping – and vermin destroying
Patent
1991-07-26
1993-01-26
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437225, 437228, 148DIG51, 156643, 156646, 156654, 156657, 427534, H01L 2100, H01L 2102, H01L 21306, H01L 21308
Patent
active
051822342
ABSTRACT:
A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative junctions within a silicon substrate and the conductive structures formed atop the substrate. A trench is formed in the upper silicon surface and a source conductive layer is deposited to electrically contact the source region as a gate conductive layer is deposited atop the gate oxide layer. The trench sidewall is profile tailored using a novel O.sub.2 -SF.sub.6 plasma etch technique. An oxide sidewall spacer is formed on the sides of the pattern definer and gate oxide structures, before depositing the conductive material. A planarizing layer is applied and used as a mask for selectively removing any conductive material deposited atop the oxide spacer. The polysilicon layer on the oxide is reduced in thickness during trenching so that any conductive material deposited atop the spacers protrude upward for easy removal of excess, conductive material. The sidewall spacers can be sized, either alone or in combination with profile tailoring of the trench, to control source-region width (i.e., parasitic pinched base width) and proximity of the source conductor to the FET channel. Electrical contact between the source conductive layer and the source regions is enhanced by forming a low-resistivity layer between them.
REFERENCES:
patent: 4412119 (1983-10-01), Komatsu et al.
patent: 4589952 (1986-05-01), Behringer et al.
patent: 4615764 (1986-10-01), Bobbio et al.
patent: 4634495 (1987-01-01), Gobrecht et al.
patent: 4729815 (1988-03-01), Leung
patent: 4741799 (1988-05-01), Chen et al.
d'Agostino, R., Plasma Etching of Si and SiO.sub.2 in SF.sub.6 -O.sub.2 mixtures, J. Appl. Phys. 52(1), Jan. 1981, pp. 162-167.
Ghandhi, S., VLSI Fabrication Principles, pp. 372-373, Wiley & Sons, 1983.
Sze, S., VLSI Technology, pp. 319, 320, 324, McGraw-Hill, 1983.
Coburn, J., Plasma-Assisted Etching, pp. 1-9, 28, 29, 36-41, Plasma Chemistry and Plasma Processing, vol. 2, No. 1, 1982.
Advanced Power Technology Inc.
Everhart B.
Hearn Brian E.
LandOfFree
Profile tailored trench etch using a SF.sub.6 -O.sub.2 etching c does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Profile tailored trench etch using a SF.sub.6 -O.sub.2 etching c, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Profile tailored trench etch using a SF.sub.6 -O.sub.2 etching c will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1412515