Fishing – trapping – and vermin destroying
Patent
1990-12-12
1993-01-26
Thomas, Tom
Fishing, trapping, and vermin destroying
437 47, 437 51, 437904, 437919, H01L 2170
Patent
active
051822237
ABSTRACT:
An integrated circuit (42) is formed in a semiconductor layer (50) having a defined area. Functional circuitry (12) is formed in semiconductor layer (50) to occupy only a portion of the defined area of semiconductor layer (50), and thus defining an unoccupied area of semiconductor layer (50). A capacitor is formed in semiconductor layer in a substantial portion of the unoccupied area.
REFERENCES:
patent: 3638301 (1972-02-01), Matsuura
patent: 3999212 (1976-12-01), Usuda
patent: 4044373 (1977-08-01), Nomiya et al.
patent: 4739378 (1988-04-01), Ferrari et al.
patent: 4785202 (1988-11-01), Toyoda
patent: 4829344 (1989-05-01), Berbotti et al.
Niehaus Jeffrey A.
Ovens Kevin M.
Barndt B. Peter
Donaldson Richard L.
Texas Instruments Incorporated
Thomas Tom
LandOfFree
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