Fishing – trapping – and vermin destroying
Patent
1991-06-26
1993-01-26
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 44, 437 58, 437200, 437913, 148DIG126, H01L 21265
Patent
active
051822229
ABSTRACT:
A method is provided for manufacturing a semiconductor device at a face of a semiconductor layer having a first conductivity type. Over the semiconductor layer and insulating therefrom a gate conductive layer is formed, which has a predetermined pattern defining an opening. A well of a second conductivity type is then implanted into the face of the semiconductor layer by self-aligning to the sidewall of the gate conductive layer. A first surface region of the first conductivity type is formed within the well and self-aligned to the sidewall of the gate conductive layer. A sacrificial sidewall layer is formed in the opening which defines a second narrower opening, so that a subsurface region of the second conductivity type may be formed within the well self-aligned to the sacrificial sidewall layer. A second surface region of the second conductivity type is then formed substantially within the first surface region and self-aligned to the sacrificial sidewall layer. The construct of the first and second surface regions is such that the second surface region at the face of the semiconductor layer is substantially surrounded by the first surface region. The sacrificial sidewall layer is removed and a thinner insulating sidewall is formed in the opening. In this manner, the second surface region as well as a portion of the first surface region substantially surrounding the first surface region are exposed. Subsequently, a source electrode contacting the exposed second surface region and the exposed first surface region substantially surrounding the second surface region at the face of said semiconductor layer is formed.
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Efland Taylor R.
Malhi Satwinder
Donaldson Richard L.
Hearn Brian E.
Kesterson James C.
Matsil Ira S.
Texas Instruments Incorporated
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