Cross-point contact-free floating-gate memory array with silicid

Details Cross-point contact-free floating-gate memory array with silicid Cross-point contact-free floating-gate memory array with silicid

1990-09-04

1992-05-05

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 41, 437 43, 437 48, 437 49, 437228, 357 235, H01L 2170, H01L 2700

Patent

active

051107538

ABSTRACT:
A contact-free floating-gate non-volatile memory cell array and process with silicided NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines have a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Isolation between wordlines and between bitlines is by thick field oxide. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by extending the gates over the thick field oxide and perhaps by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The resulting structure is a dense cross-point array of progammable memory cells.

REFERENCES:
patent: 4422092 (1983-12-01), Guterman
patent: 4597060 (1986-06-01), Mitchell et al.
patent: 4652897 (1987-03-01), Okuyama et al.
patent: 4763177 (1988-08-01), Paterson
patent: 4849369 (1989-07-01), Jeuch et al.
patent: 4855800 (1989-08-01), Esquivel et al.
patent: 4891326 (1990-01-01), Koyanagi

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