Method and apparatus for adaptive clock recovery

Details Method and apparatus for adaptive clock recovery Method and apparatus for adaptive clock recovery

1993-04-28

1995-03-07

Safourek, Benedick V.

Multiplex communications

Wide area network

Packet switching

370108, 375371, H04J 306

Patent

active

053964926

ABSTRACT:
An adaptive clock recovery arrangement for deriving a synchronous clock from an asynchronous, packet stream such as an asynchronous transfer mode (ATM) cell stream. The deviation in the magnitude of information stored in a first-in-first-out memory is continually monitored, and the synchronous clock frequency, referred to as the adaptive line clock frequency, is adjusted in a plurality of modes, under the control of a processor. The adjustment is made in response to a detected increasing condition of the monitored deviation. The adjustments are open-loop adjustments made without continually adjusting the adaptive line clock frequency based on the monitored deviation. Damping is substantially reduced compared with "conventional" PLL arrangements because the open-loop adjustments result in a rapid frequency correction with perfect or nearly perfect deadbeat damping, i.e. without the frequency oscillations that continue after the correct frequency is reached in closed-loop arrangements.

REFERENCES:
patent: 3754098 (1973-08-01), Abramson et al.
patent: 4759041 (1988-07-01), Anderson et al.
patent: 5142529 (1992-08-01), Parruck et al.
R. C. Lau, "A Clock Recovery Scheme for ATM Circuit Emulsion", Bellcore, Oct. 10, 1988.
K. Yamazaki, "Introduction to AAL type 1", Document AVC-214, Mar. 9, 1992.

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