Digital filter circuit that minimizes holding errors transmitted

Details Digital filter circuit that minimizes holding errors transmitted Digital filter circuit that minimizes holding errors transmitted

1993-11-23

1995-03-07

Mai, Tan V.

Boots, shoes, and leggings

364602, G06G 702, G06J 100

Patent

active

053964462

ABSTRACT:
A filter circuit that controls holding errors so that such errors are held to a minimum. In the filter circuit, multipliers of multiplication circuits are stored in a shift register and multiplication is successively executed with various multipliers in a multiplication circuit by circulating multipliers in the shift register.

REFERENCES:
patent: 4316258 (1982-02-01), Berger
patent: 4476539 (1984-10-01), Tamori et al.
patent: 4605913 (1986-08-01), Pfleiderer et al.
patent: 4700345 (1987-10-01), Morcom et al.
patent: 5272663 (1993-12-01), Jones et al.
Massara, "Synthesis of Low-Passs Forms", The electrical Engineering Handbook pp. 674-691, undated.

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