Method for characterizing the upset response of CMOS circuits us

Details Method for characterizing the upset response of CMOS circuits us Method for characterizing the upset response of CMOS circuits us

1992-10-05

1995-03-07

Wieder, Kenneth A.

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

With rotor

365154, 437 26, G01R 104

Patent

active

053961692

ABSTRACT:
A method for predicting the SEU susceptibility of a standard-cell D-latch using an alpha-particle sensitive SRAM, SPICE critical charge simulation results, and alpha-particle interaction physics. A technique utilizing test structures to quickly and inexpensively characterize the SEU sensitivity of standard cell latches intended for use in a space environment. This bench-level approach utilizes alpha particles to induce upsets in a low LET sensitive 4-k bit test SRAM. This SRAM consists of cells that employ an offset voltage to adjust their upset sensitivity and an enlarged sensitive drain junction to enhance the cell's upset rate.

REFERENCES:
patent: 4529884 (1985-07-01), Wolicki et al.
Zoutendyk et al., "Empirical Modelling of Single-Event Upset (SEU) in NMOS Depletion-Mode-Load Static RAM (SRAM) Chips." IEEE Transactions on Nuclear Science, vol. NS-33, No. 6, pp. 1581-1585, Dec. 1986.

Affiliated with

Also associated with

Rating

Method for characterizing the upset response of CMOS circuits us does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for characterizing the upset response of CMOS circuits us, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for characterizing the upset response of CMOS circuits us will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1408705