Low power clock driver

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307208, 307260, 328 61, H03K 100, H03K 326, H03K 400, H03K 501

Patent

active

040114686

ABSTRACT:
A low power dissipation circuit for generating clock pulses comprises a plurality of solid state devices which are normally off and draw only leakage current in their quiescent state. The clock pulse is started by a signal to a set side driver and is stopped by a signal to a reset side driver. The input drivers remain on only during the time they are being driven. The output drivers for generating the clock pulse comprises a pair of switching transistors which remain on only while the clock switching pulses are being generated.

REFERENCES:
patent: 3104330 (1963-09-01), Hamilton
patent: 3233113 (1966-02-01), Apple et al.
patent: 3523197 (1970-08-01), Salzer
patent: 3662191 (1972-05-01), Aley
patent: 3728559 (1973-04-01), Spann et al.
patent: 3824408 (1974-07-01), Brunel
patent: 3904894 (1975-09-01), Ciolli

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