Insulated gate bipolar transistor with reduced susceptibility to

Details Insulated gate bipolar transistor with reduced susceptibility to Insulated gate bipolar transistor with reduced susceptibility to

1992-12-14

1995-03-07

Loke, Steven Ho Yin

Active solid-state devices (e.g., transistors, solid-state diode

Regenerative type switching device

Combined with field effect transistor

257133, 257147, 257212, 257342, H01L 2974, H01L 31111, H01L 2358, H01L 2976

Patent

active

053960874

ABSTRACT:
A latch-up free insulated gate transistor includes an anode region electrically connected to an anode contact, a first base region on the anode region, a second base region on the first base region, connected to a cathode contact, an insulating region on the second base region and a field effect transistor on the insulating region, electrically connected between the cathode contact and the first base region. The field effect transistor provides an electrical connection between the first base region and the cathode contact in response to a turn-on bias signal. The insulating region prevents electrical conduction between the second base region and the field effect transistor and, in particular, suppresses minority carrier injection from the second base region to the source of the field effect transistor which is electrically connected to the cathode contact. The prevention of minority carrier injection reduces the likelihood of parasitic latch-up by cutting-off the regenerative P-N-P-N path that would otherwise exist between the anode and cathode. The insulating region is selected from the group consisting of SiO.sub.2, Si.sub.3 N.sub.4, Al.sub.2 O.sub.3 and MgAl.sub.2 O.sub.4 and is preferably formed using SIMOX processing techniques.

REFERENCES:
patent: 4760431 (1988-07-01), Nakagawa et al.
patent: 4914496 (1990-04-01), Nakagawa et al.
patent: 4928155 (1990-05-01), Nakagawa et al.
patent: 4954869 (1990-09-01), Bauer
patent: 4956690 (1990-09-01), Kato
patent: 4959703 (1990-09-01), Ogura et al.
patent: 4963972 (1990-10-01), Shinobe et al.
patent: 5014102 (1991-05-01), Adler
patent: 5047813 (1991-09-01), Harada
patent: 5086323 (1992-02-01), Nakagawa et al.
patent: 5089864 (1992-02-01), Sakurai
patent: 5091766 (1992-02-01), Terashima
patent: 5093701 (1992-03-01), Nakagawa et al.
patent: 5099300 (1992-03-01), Baliga
patent: 5105244 (1992-04-01), Bauer
patent: 5144401 (1992-09-01), Ogura et al.
patent: 5241194 (1993-08-01), Baliga
Baliga, Chang, Shafer and Smith, "The Insulated Gate Transistor (IGT) A New Power Switching Device," IEEE Industry Applications Society Meeting Digest, pp. 794-803, 1983.
Baliga, "Analysis of the Output Conductance of Insulated Gate Transistors," IEEE Electron Device Letters, vol. EDL-7, No. 12, pp. 686-688, Dec. 1986.
Mogro-Campero, Love, Chang and Dyer, "Shorter Trun-Off Times in Insulated Gate Transistors By Proton Implantation," IEEE Electron Device Letters, vol. EDL-6, No. 5, pp. 224-226, May, 1985.
Chow and Baliga, "Comparison of 300-, 600-, and 1200-V n-Channel Insulated Gate Transistors," IEEE Electron Device Letters, vol. EDL-6, No. 4, pp. 161-163, Apr. 1985.
Kuo, Choi, Giandomenico, Hu, Sapp, Sassaman and Bregar, "Modeling the Turn-Off Characteristics of the Bipolar-MOS Transistor," IEEE Electron Device Letters, vol. EDL-6, No. 5, pp. 211-214, May, 1985.
Baliga, "Analysis of Insulated Gate Transistor Turn-Off Characteristics," IEEE Electron Device Letters, vol. EDL-6, No. 2, pp. 74-77, Feb. 1985.
Chow, Baliga and Gray, "A Self-Aligned Short Process For Insulated Gate Transistors," IEEE, IEDM-85, pp. 146-149, 1985.
Nakagawa, Yamaguchi, Watanabe, Ohashi and Kurata, "Experimental and Numerical Study of Non-Latch-Up Bipolar-Mode MOSFET Characteristics," IEEE, IEDM-85, pp. 150-153, 1985.
Chow, Baliga and Chang, "The Effect of Channel Length and Gate Oxide Thickness on the Performance of Insulated Gate Transistors," IEEE Transactions on Electron Devices, vol. ED-32, No. 11, p. 2554, Nov. 1985.
Nakagawa, Ohashi, Kurata, Yamaguchi and Watanbe, "Non-Latch-Up 1200V 75A Bipolar-Mode MOSFET with Large ASO," IEEE, IEDM-84, pp. 860-861, 1984.
Chang, Pifer, Yilmaz, Dyer, Baliga, Chow and Adler, "Comparison Of N and P Channel IGTs," IEEE, IEDM-84, pp. 278-281, 1984.
Baliga, Adler, Gray and Love, "Suppressing Latchup in Insulated Gate Transistors," IEEE Electron Device Letters, vol. EDL-5, No. 8, pp. 323-325, Aug. 1984.
Chang, Pifer, Baliga, Adler and Gray, "25 AMP, 500 Volt Insulated Gate Transistors," IEEE, IEDM-83, pp. 83-86, 1983.
Russell, A. M. Goodman, L. A. Goodman and Neilson, "The COMFET-A New High Conductance MOS-Gated Device," IEEE Electron Device Letters, vol. EDL-4, No. 3, pp. 63-65, Mar. 1983.
A. M. Goodman, Russell, L. A. Goodman, Nuese and Neilson, "Improved COMFETS with Fast Switching Speed and High-Current Capability," IEEE, IEDM-83, pp. 79-82, 1983.
Baliga, Adler, Gray and Love, "The Insulated Gate Rectifier (IGR): A New Power Switching Device," IEEE, IEDM-82, pp. 264-267, 1982.
Temple, "MOS Controlled Thyristors (MCT's)", IEDM-84, pp. 282-285, 1984.
Baliga, Adler, Love, Gray and Zommer, "The Insulated Gate Transistor: A New Three-Terminal MOS-Controlled Bipolar Power Device", IEEE Transactions on Electron Devices, vol. ED-31, No. 6, pp. 821-828, Jun. 1984.
Baliga and Chang, "The MOS Depletion-Mode Thyristor: A New MOS-Controlled Bipolar Power Device," IEEE Electron Device Letters, vol. 8, No. 8, pp. 411-413, Aug. 1988.
Baliga, "The MOS-Gated Emitter Switched Thyristor," IEEE Electron Device Letters (reprint), vol. 11, No. 2, pp. 75-77, Feb. 1990.
Nandakumar, Baliga, Shekar, Tandon and Reisman, "A New MOS-Gated Power Thyristor Structure with Turn-Off Achieved by Controlling the Base Resistance," IEEE Electron Letters, vol. 12, No. 5, pp. 227-229, May, 1991.
Shekar, Baliga, Nandakumar, Tandon and Reisman, "Characteristics of the Emitter-Switched Thyristor", IEEE Transactions on Electron Devices, vol. 38, No. 7, pp. 1619-1623, Jul. 1991.
Nandakumar, Baliga, Shekar, Tandon and Reisman, "The Base Resistance Controlled Thyristor (BRT) `A New MOS Gated Power Thyristor`", IEEE, pp. 138-141, 1991.
Shekar, Baliga, Nandakumar, Tandon and Reisman, "Experimental Demonstration of the Emitter Switched Thyristor", pp. 128-131.

Affiliated with

Also associated with

Rating

Insulated gate bipolar transistor with reduced susceptibility to does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Insulated gate bipolar transistor with reduced susceptibility to, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Insulated gate bipolar transistor with reduced susceptibility to will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1408088