Stress-free isolation layer

Details Stress-free isolation layer Stress-free isolation layer

1994-05-11

1995-03-07

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 70, 437 72, 437 73, 437 67, 148DIG50, H01L 2176

Patent

active

053957903

ABSTRACT:
A method of fabricating a stress-free isolation layer for semiconductor integrated circuit that solves the problems of crystalline defects and the degraded characteristics of devices due to the presence of structural stresses. Partial trench etching is employed to form at least one narrow trenches, followed by anneal-treating to release stress and eliminate crystalline defects therein. Isolating material is then filled into the narrow trenches to form a complete stress-free isolation layer.

REFERENCES:
patent: 4211582 (1980-07-01), Horng et al.
patent: 5204280 (1993-04-01), Dhong et al.
patent: 5292689 (1994-03-01), Cronin et al.
patent: 5308786 (1994-05-01), Lur et al.

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