First in first out activity queue for a cache store

Boots – shoes – and leggings

Patent

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Details

G06F 1300, G11C 906

Patent

active

041953401

ABSTRACT:
A first in-first out buffer memory coupled to a system bus receives all information transferred over the bus. Logic associated with the buffer memory tests if the information received is intended to update main memory or is in response to a cache request. The information is written into cache if the main memory address location is stored in a cache directory. The information received in response to a cache request is stored in a cache data buffer. Other information is discarded.

REFERENCES:
patent: 3840862 (1974-10-01), Ready
patent: 4084234 (1978-04-01), Calle et al.

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