Verification method of logical circuit layout patterns

Details Verification method of logical circuit layout patterns Verification method of logical circuit layout patterns

1992-01-22

1994-10-25

Ramirez, Ellis B.

Boots, shoes, and leggings

364578, 364490, G06F 1520, G06F 1560

Patent

active

053595343

ABSTRACT:
A logical circuit layout pattern verification method. Verification of a logical circuit layout pattern is performed by: adding the parasitic capacitance of a layout pattern of a logical circuit to a load capacitance of logic gates, calculating an output value of the logical circuit based on the total capacitance, and verifying the layout pattern by comparing the output value and the expected output value calculated at initial design. In the calculation of the delay time of the logic gate, the delay time corresponding to discrete representative values of the load capacitance are first calculated, the functions describing the relationship between the load capacitance and the delay time are calculated using the delay time, and based on the function, the delay time corresponding to the load capacitance having continuous values is calculated. With the method, malfunctioning of the circuit caused by delay time is predictable.

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patent: 5197015 (1993-03-01), Hartoog et al.
Brechling et al; "Width-To-Length Ratio Design Program For Interacting Dynamic FET Circuits"; IBM Tech. Disc. vol. 16, No. 6 Nov. 1973.
Garner; "Computer Aided Design of VLSI Saves Man-Hours, Reduces Errors"; Control Engineering, Apr. 1981.

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